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INTEGRATED CIRCUITS
74LVC169 Presettable synchronous 4-bit up/down binary counter
specification Supersedes data of 1996 Aug 23 IC24 Data Handbook 1998 May 20
Philips Semiconductors
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
FEATURES
* Wide supply voltage range of 1.2 V to 3.6 V * In accordance with JEDEC standard no. 8-1A * Inputs accept voltages up to 5.5 V * CMOS low power consumption * Direct interface with TTL levels * Synchronous counting and loading * Up/down counting * Modular 16 binary counter * Two count enable inputs for n-bit cascading * Built-in lookahead carry capability * Presettable for programmable operation * Positive-edge triggered clock
DESCRIPTION
The 74LVC169 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
The 74LVC169 is a synchronous presettable binary counter which features an internal lookahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The lookahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 fmax = _______________________________ tp(max) (CP to TC) + tSU (CEP to CP)
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; TR = TF 2.5ns SYMBOL PARAMETER Propagation delay CP to Qn CP to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS CL = 50 pF VCC = 3.3V TYPICAL 5.0 6.5 5.3 200 5.0 42 UNIT
tPHL/tPLH
ns
fMAX CI CPD
MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi + (CL x VCC2 x fo ) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo ) = sum of the outputs 2. The condition is V1 = GND to VCC
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC169 D 74LVC169 DB 74LVC169 PW NORTH AMERICA 74LVC169 D 74LVC169 DB 74LVC169PW DH DWG NUMBER SOT109-1 SOT338-1 SOT403-1
1998 May 20
2
853-1866 19421
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
PIN CONFIGURATION
U/D CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
PIN DESCRIPTION
PIN NUMBER 1 2 3,4,5,6 7 8 9 10 SYMBOL U/D CP D0 to D3 CEP GND PE CET Q0 to Q3 TC VCC FUNCTION up/down control input clock input (LOW-to-HIGH, edge-triggered) data inputs count enable inputs (active LOW) ground (0V) parallel enable input (active LOW) count enable carry input (active LOW) flip-flop outputs terminal count output (active LOW) positive supply voltage
SF00766
LOGIC SYMBOL
3 4 5 6
14,13,12,11 15 16
9 1 2 7 10
PE U/D
D0
D1
D2
D3
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 16 TC 15 9
CP CEP CET Q0 Q1 Q2 Q3
M1 [LOAD] M2 [COUNT]
1
M3 [UP] M4 [DOWN] 15
10 14 13 12 11 7 2 VCC = Pin 16 GND = Pin 8
G5 G6 2, 3, 5, 6+/C7 2, 4, 5, 6-
3, 5 CT=15 4, 5 CT=0
SF00786
3 4 5 6 1, 7D [1] [2] [4] [8] 14 13 12 11
SF00787
1998 May 20
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
STATE DIAGRAM
0 1 2 3 4
TYPICAL TIMING SEQUENCE
MR PE
15
5
D0 D1
14
6
D2 D3
13
7 CP
12
11
10
9
8
CEP CET
COUNT DOWN COUNT UP
Q0
SF00788
Q1 Q2 Q3
FUNCTION TABLE
OPERATING MODES Parallel load (DnQn) Count Up (increment) Count Down (decrement) Hold (do nothing) INPUTS CP U/D X X h l X X CEP X X l l h X CET X X l l X X PE l X h h h h Dn l X X X X X OUTPUTS Qn L H Count Up Count Down qn qn TC * * * * * H
TC 12 13 14 15 0 1 2 INHIBIT RESET PRESET COUNT
SY00069
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one, and two; inhibit
H = High voltage level steady state h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level steady state l = Low voltage level one setup time prior to the Low-to-High clock transition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition X = Don't care = Low-to-High clock transition * = The TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).
1998 May 20
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
LOGIC DIAGRAM
3 D0
D
Q 14 Q0
CP Q
D1
4
D
Q 13 Q1
CP Q
D2
5
D
Q 12 Q2
CP Q
D3 PE
6
D
Q 11 Q3
9
CP Q
7 CEP 10 CET 2 1 15 TC
CP U/D
VCC = Pin 16 GND = Pin 8
SF00789
1998 May 20
5
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
APPLICATION
CP U/D PE D0 PE U/D CP CEP CET Q0 Q1 Q2 Q3 TC D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
PE U/D CP CEP CET
PE U/D CP TC CEP CET
PE U/D CP TC CEP CET
TC
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
LEAST SIGNIFICANT 4-BIT COUNTER
MOST SIGNIFICANT 4-BIT COUNTER
SF00790
Synchronous multistage counting scheme
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC +85 20 10 UNIT V V V C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +5.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 500 500 mW UNIT V mA V mA V mA mA C
PTOT
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 20
6
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II ICC ICC Input leakage current Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 "0 1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*1.0 0.40 0.20 0.55 "5 10 500 A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
1998 May 20
7
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = -40_C to +85_C LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN. tPHL/tPLH tPHL/tPLH tPHL/tPLH tPHL/tPLH tW tsu tsu tsu tsu propagation delay CP to Qn propagation delay CP to TC propagation delay CET to TC propagation delay U/D to TC clock pulse width HIGH or LOW set-up time Dn to CP set-up time
PE
VCC = 2.7V MIN. MAX. 9.5
VCC = 1.2V TYP 24
UNIT
TYP1 5.0
MAX. 8.5
1
-
ns
1
-
6.5
10.8
-
12.8
30
ns
2
-
5.3
8.7
-
9.7
19
ns
4
-
5.7
9.5
-
10.5
24
ns
1
4.0
1.2
-
5.0
-
-
ns
3
2.5
1.0
-
3.0
-
-
ns
to CP
3
3.0
1.2
-
3.5
-
-
ns
set-up time U/D to CP set-up time CEP, CET to CP hold time
5
5.5
2.8
-
6.5
-
-
ns
5
4.5
2.1
-
5.5
-
-
ns
th
Dn, PE, CEP, CET, U/D to CP maximum clock pulse frequency
3 and 5
0
*2.5
-
0
-
-
ns
fmax
1
125
200
-
110
-
-
MHz
NOTE: 1. These typical values are measured at VCC = 3.3V and Tamb = 25C.
1998 May 20
8
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V VM = 0.5 S VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load.
1/fMAX VI CP INPUT GND VM VI tw tPHL VM tPLH CP INPUT GND tSU VI Dn INPUT VM th tSU th VM VI PE INPUT GND VM tSU th tSU th
VOH Qn, TC OUTPUT VOL
SY00071
GND The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency.
SC00137
Waveform 4. Setup and hold times for the input (Dn) and parallel enable input (PE). VI
CET
VM tPHL
VM tPLH VM VM
CEP, CET INPUT GND
VM
TC
tsu
th
tsu
th
VI
CP INPUT VM VM GND
SF00792
Waveform 2. Input (CET) to output (TC) propagation delays and output transition times. NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SC00138
Waveform 5.
U/D VM tPHL TC VM VM tPLH VM
CEP and CET setup and hold times.
TEST CIRCUIT
VCC S1 2 * VCC Open GND
SF00793
Waveform 3. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times.
500 VI PULSE GENERATOR RT D.U.T. VO
50pF
CL
500
SWITCH POSITION
TEST tPLH/tPHL S1 Open VCC < 2.7V 2.7-3.6V VI VCC 2.7V
SV00903
Waveform 6.
Load circuitry for switching times.
1998 May 20
9
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 May 20
10
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 May 20
11
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 May 20
12
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
NOTES
1998 May 20
13
Philips Semiconductors
Product specification
Presettable synchronous 4-bit up/down binary counter
74LVC169
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04498
Philips Semiconductors

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